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Nathan Vander wilt (@natevw) · 04/2017 · Tröts: 1.088 · Folger: 275
Di 21.05.2024 20:22
kind of fun to track down "unpossible" things — like surely if you start an ADC sample conversion it will complete, right?
unless there's an extra bit not in your mental model that **can** prevent the conversion from starting… "(See Note)"
screenshot of Figure 22-1 of page 844 of slau356i.pdf it's a big logic diagram but tucked in a corner of the middle is my own annotation circling a `SHI_EN` signal input that gets AND-gated with the main SHI signal before the latter actually would start the sample timer. next to that former "enable" alternate signal in the original PDF is a parenthetical warning to "See Note" about it.
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